Integrated clock gating cell using a low area and a low power latch
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United States of America Patent
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Jan 26, 2016
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N/A
app pub date -
Sep 29, 2014
filing date -
Sep 29, 2014
priority date (Note) -
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Abstract
The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.
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