Dual register data path architecture with registers in a data file divided into groups and sub-groups
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United States of America Patent
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Nov 4, 2014
Grant Date -
Mar 29, 2012
app pub date -
Sep 15, 2011
filing date -
Sep 28, 2010
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Abstract
A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
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