Hardware implementation of a Galois field multiplier
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United States of America Patent
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Feb 11, 2014
Grant Date -
Mar 10, 2011
app pub date -
Sep 3, 2010
filing date -
Sep 8, 2009
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Abstract
An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n−1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n−1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n−1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles.
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