Method and apparatus for modeling processor-based circuit models
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United States of America Patent
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Jul 24, 2012
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app pub date -
Sep 29, 2008
filing date -
Sep 29, 2008
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Abstract
Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.
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