Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system
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United States of America Patent
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May 26, 2009
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N/A
app pub date -
Dec 5, 2006
filing date -
Dec 5, 2006
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Abstract
Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is specified. The at least one shared memory is associated with the at least one processor. A memory map associated with the at least one shared memory and a bus adapter for coupling the memory map to the at least one processor are automatically generated.
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