High-frequency switching device with reduced harmonics
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United States of America Patent
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Feb 17, 2009
Grant Date -
Oct 18, 2007
app pub date -
Jul 24, 2006
filing date -
Apr 17, 2006
priority date (Note) -
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status (Latency Note)
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Abstract
According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.
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