Reducing input capacitance of high speed integrated circuits

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United States of America Patent

PATENT NO 7535689
APP PUB NO 20080316662A1
SERIAL NO

11821005

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Abstract

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An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abdulla, Mostafa Naguib Rancho Cordova , US 26 210
Christensen, Gregory V Lehi , US 1 4
Cui, Ming Dong Shanghai , CN 1 4
He, Jiangqi Gilbert , US 74 1168
Lu, Daoqiang Chandler , US 127 2004
Tang, Jiamiao Shanghai , CN 13 471
Zeng, Xiang Yin Shanghai , CN 29 452

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